Renesas Electronics /R7FA6T3BB /CANFD_B /CFDGFDCFG

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Interpret as CFDGFDCFG

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (0)RPED 0 (00)TSCCFG

TSCCFG=00, RPED=0

Description

Global FD Configuration Register

Fields

RPED

RES Bit Protocol Exception Disable

0 (0): Protocol exception event detection enabled

1 (1): Protocol exception event detection disabled

TSCCFG

Timestamp Capture Configuration

0 (00): Timestamp capture at the sample point of SOF (start of frame)

1 (01): Timestamp capture at frame valid indication

2 (10): Timestamp capture at the sample point of RES bit

3 (11): Reserved

Links

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